A network on a chip (NOC) is a novel integrated circuit architecture that applies a network-based architecture to a single chip to create a unique processing unit. A typical NOC includes a plurality of integrated processor (IP) blocks coupled to one another via the network. NOC processing units typically distribute (i.e., allocate) various parts of a job to different hardware threads of one or more IP blocks to be executed by the one or more IP blocks in the NOC processing unit, where the distribution typically includes transmitting data packets (i.e., messages) including one or more data words between one or more IP blocks of the NOC. With the number of IP blocks in the standard computer systems expected to rise, efficiently handling workload distribution and message communication has become increasingly demanding.
Moreover, during processing of a job, IP blocks generally communicate data therebetween as directed by the tasks of the workload, where an IP block may receive data from one or more transmitting IP blocks. Data communicated from one IP block to another is generally stored in buffer associated with the receiving IP block. With multiple IP blocks potentially transmitting to a single IP block, in conventional systems deadlocks, livelocks and storage starvation issues may arise if inadequate buffer storage is available for the receiving IP block. In some conventional systems, once a buffer for an IP block becomes full, the receiving IP block may drop transmitted data packets (i.e., fail to store received data packets). To address these issues, conventional systems generally overbuild buffers such that each IP block is associated with buffer space that exceeds hardware/software requirements. While overbuilding a buffer may address some problems associated with communications for distributed processing systems, as the number of IP blocks is expected to rise, the increasing amount of space dedicated to buffers in an NOC configuration becomes an increasingly wasteful solution.
A continuing need exists in the art for a manner of communicating data messages in computing systems including a plurality of interconnected integrated processor blocks.